Complementary metal oxide semiconductor (CMOS) technology has come into standard use in semiconductor device manufacturing. CMOS circuits include combinations of p-type MOS devices and n-type MOS devices, and are characterized by low power consumption and high packaging density. A significant trend in semiconductor device manufacturing is toward reduced device dimensions, resulting in increased packaging density and increased circuit complexity. As device dimensions are reduced, processes become more complex. Notwithstanding the increased complexity, processing costs must be carefully controlled.
A current front end of line (FEOL) CMOS process typically involves the use of eight patterned masks, six of which are implant masks. First and second implant masks are used to dope the substrate surface by n-type and p-type ion implantation prior to formation of gate electrodes. These doped regions are called n-wells and and p-wells, and can contain multiple dopant profiles, such as wells, channel stops, punch through stops and threshold adjusts. After formation of gate electrodes, a third implant mask is used for a p+ source/drain extension implant and an optional halo implant, and a fourth implant mask is used for an n+ source/drain extension implant and an optional halo implant. After deposition and etching of a sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes, a fifth implant mask is used for a p+ source/drain implant, and a sixth implant mask is used for an n+ source/drain implant. It is estimated that each mask adds approximately 30 dollars to the cost of an eight inch semiconductor wafer. In addition, multiple implant masks increase processing time and increase the risk of processing error.
A CMOS process utilizing post gate implantation of wells, channels and source/drains is disclosed by H. Mikoshiba et al in "A Novel CMOS Process Utilizing After-Gate-Implantation Process", IEEE, 1986 Symposium on VLSI Technology, June 1986, pages 41-42.
A technique for forming super-steep retrograde channel profiles using ion implantation through the gate is disclosed by Y. V. Ponomarev et al in "Channel Profile Engineering of 0.1 .mu.m-Si MOSFET's by Through-the-Gate Implantation", IEEE, IEDM-98, Dec. 1998, pages 635-638.
A shallow junction well FET structure, wherein ion implantations for a shallow p-well and n-well were performed through the gate electrodes, is disclosed by H. Yoshimura et al in "New CMOS Shallow Junction Well FET Structure (CMOS-SJET) For Low Power-Supply Voltage", IEEE, IEDM-92, Dec. 1992, pages 35.8.1-35.8.4.
A CMOS fabrication process wherein CMOS vertically modulated wells are constructed by using clustered MeV ion implantation to form a structure having a buried implanted layer for lateral isolation is disclosed in U.S. Pat. No. 5,501,993 issued Mar. 26, 1996 to Borland; U.S. Pat. No. 5,814,866 issued Sep. 29, 1998 to Borland; and U.S. Pat. No. 5,821,589 issued Oct. 13, 1998 to Borland.
All of the known prior art semiconductor fabrication processes have one or more disadvantages, including a high degree of complexity and high cost. Accordingly, there is a need for simplified semiconductor fabrication processes which are capable of producing high density devices at low cost.